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august 200 4 asm4sstvf16857 rev 2 . 0 alliance semiconductor 2575, augustine drive ? santa clara, ca ? tel: 408.855.4900 ? fax: 408.855.4999 ? www.alsc.com notice: the information in this document is subject to change without notice. ddr 14 - bit registered buffer features ? ? ? ? ? product description the asm4sstvf16857 is a universal 14 - bit register (d f/f based), designed for 2.3v to 2.7v v dd . the device supports sstl_2 i/o levels, and is fully compliant with the jede c jc40, jc42.5 ddr i specifications covering pc1600, pc2100, pc2700, and pc3200 operational ranges. 14 - bit refers to 2q outputs for each d input - designed for use in stacked registers (stacked memory devices), buffered dimm applications. data flow from d to q is controlled by the differential clock (clk/clkb) along with a controlled reset (resetb). the positive edge of clk is used to trigger the data transfer, and clkb is used to maintain sufficient noise margins, whereas the resetb input is designed and intended for use at power - up. the asm4sstvf16857 supports a low power standby mode of operation. a logic low level at resetb, assures that all internal registers and outputs (q) are reset to a logic low state, and that all input receivers, data (d) buff ers, and clock (clk/clkb) are switched off. note that resetb should be supported with a lvcmos level at a valid logic state since vref may not be stable during power - up. to ensure that outputs are at a defined logic state before a stable clock has been su pplied, resetb must be held at a logic low level during power - up. in the jedec defined registered ddr dimm application, resetb is specified to be asynchronous with respect to clk/clkb; therefore, no timing relationship can be guaranteed between the tw o signals. when entering a low - power standby mode, the register will be cleared and the outputs will be driven to a logic low level quickly relative to the time to disable the differential input receivers. this ensures there are applications ? ? ? ? ?
a ugust 200 4 asm4sstvf16857 r ev 2.0 ddr 14 - bit registered buffer 2 of 16 block diagram pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 q1 q2 gnd vddq q3 q4 q5 gnd vddq q6 q7 vddq gnd q8 q9 vddq gnd q10 q11 q12 vddq gnd q13 q14 d1 d2 gnd vdd d3 d4 d5 d6 d7 clkb clk vdd gnd vref resetb d8 d9 d10 d11 d12 vdd gnd d 13 d14 48 - pin tssop & tvsop 6.10 mm body, 0.50 mm pitch - tssop 4.40mm body, 0.40mm pitch - tssop (tvsop) a s m 4 s s t v f 1 6 8 5 7 clk clkb resetb d1 vref r clk d1 q1 to 13 other channels asm4sstvf16857 38 39 34 48 35
a ugust 200 4 asm4sstvf16857 r ev 2.0 ddr 14 - bit registered buffer 3 of 16 pin description s pin # pin name type description 1, 2, 5, 6, 7, 10, 11, 14, 15, 18, 19, 20, 23, 24 q (14:1) o data output. 3, 8, 13, 17, 22, 27, 36, 46 gnd p ground to entire chip. 4, 9, 12, 16, 21 vddq p output supply voltage. 25, 26, 29, 30, 31, 32, 33, 40, 41, 42, 43, 44, 47, 48 d(14:1) i data input. 38 clk i positive clock input. 39 clkb i negative clock input. 28, 37, 45 vdd p core supply voltage. 34 resetb i rest active low. 35 vref i input reference voltage. truth table 1 inputs q outputs resetb clk clkb d q l x or floating x or floating x or floating l h h h h l l h l or h l or h x q 0 2 note:
a ugust 200 4 asm4sstvf16857 r ev 2.0 ddr 14 - bit registered buffer 4 of 16 absolute maximum ratings parameter min max unit storage temperature - 65 +150 c supply voltage - 0.5 3.6 v input voltage 1 - 0.5 v dd + 0.5 v output voltage 1,2 - 0.5 v dd + 0.5 v input clamp curren t 50 ma output clamp current 50 ma continuous output current 50 ma vdd, vddq or gnd current/pin 100 ma package thermal impedance 3 55 c/w note: 1. the input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. this current will flow only when the output is in the high state level v 0 > v ddq. 3. the package thermal impedance is calculated in accordance with jesd 51. these are stress ratings only and functional operation is not implied. exposure to absolute maximum ratings for prolonged periods can affect device reliability.
a ugust 200 4 asm4sstvf16857 r ev 2.0 ddr 14 - bit registered buffer 5 of 16 recommended operating conditions guaranteed by design. not 100% tested in production. parameter description min typ max unit v dd supply voltage 2.3 2.5 2.7 v pc1600, pc2100, pc2700 2.3 2.7 v ddq output s upply voltage pc3200 2.5 2.7 v pc1600, pc2100, pc2700 1.15 1.25 1.35 v ref reference voltage (v ref = v ddq /2) pc3200 1.25 1.3 1.35 v v tt termination voltage v ref - 0.04 v ref v ref + 0.004 v v i input voltage 0 v dd v v ih(dc) dc input high voltage v ref + 0.15 v v ih(ac) ac input high voltage v ref + 0.31 v v il(dc) dc input low voltage v ref - 0.15 v v il(ac) ac input low voltage data inputs v ref - 0.31 v v ih input high voltage level 1.7 v v il inpu t low voltage level resetb 0.7 v v icr common mode input range clk 0.97 1.53 v v id differential input voltage clkb 0.36 v v ix cross - point voltage of differential clock pair (v ddq /2) - 0.2 (v ddq /2) +0.2 v i oh high - level output current - 20 ma i ol low - l evel output current 20 ma t a operating free - air temperature 0 70 c
a ugust 200 4 asm4sstvf16857 r ev 2.0 ddr 14 - bit registered buffer 6 of 16 dc electrical characteristics - pc1600, pc2100, pc2700 t a = 0c to 70c, v dd = 2.5 0.2v, and v ddq = 2.50.2v (unless otherwise stated) guaranteed by design. not 100% production test ed. symbol parameter test conditions v dd min typ max units v ik i i = - 18 ma 2.3 v - 1.2 v i oh = - 100 ? a 2.3 v to 2.7 v v dd - 0.2 v v oh i oh = - 16 ma 2.3 v 1.95 v i ol = 100 ? a 2.3 v to 2.7 v 0.2 v v ol i ol = 16 ma 2.3 v 0.35 v i i all inpu ts v i = v dd or gnd 2.7 v 5 ? a standby (static) resetb = gnd 2.7 v 0.01 ? a i dd operating (static) v i = v ih(ac) or v il(ac) , resetb = v dd 2.7 v 25 ma dynamic operating (clock only) resetb = v dd , v i = v ih(ac) or v il(ac) , clk and clk b switching 50% duty cycle 2.7 v 28 ? a/clock mhz i ddd dynamic operating (per each data input) resetb = v dd , v i = v ih(ac) or v il(ac) , clk and clkb = switching 50% duty cycle; one data input switching at half clock frequency, 50% duty cycle i o = 0 2.7 v 15 ?? /c lock mhz/data input r oh output high i oh = - 20 ma 2.3 v to 2.7 v 7 13.5 20 ? r ol output low i ol = 20 ma 2.3 v to 2.7 v 7 20 ? r o(d) |r oh - r ol | each separate bit i o = 20 ma, t a = 25 ? c 2.5 v 4 ? data inputs 2.5 v 2.5 3.5 pf clk & clkb v i = v ref 310 mv, v icr = 1.25 v, v i( pp) = 360 mv 2.5 v 2.5 3.5 pf c i resetb v i = v dd or gnd 2.5v 2.5 3.5 pf
a ugust 200 4 asm4sstvf16857 r ev 2.0 ddr 14 - bit registered buffer 7 of 16 dc electrical characteristics - pc3200 t a = 0c to 70c, v dd = 2.6 0.2v, and v ddq = 2.60.2v (unless otherwise stated) guaranteed by design. not 100% production tested. symbol parameters test conditions v dd (v) min typ max units v ik i i = - 18 ma 2.5 - 1.2 v i oh = - 100 ? a 2.5 v to 2.7 v dd - 0.2 v v oh i oh = - 8 ma 2.5 1.95 v i ol = 100 ? a 2.5 v to 2.7 0.2 v v ol i ol = 8 ma 2.5 0.35 v i i all inputs v i = v dd or gnd 2.7 5 ? a standby (static) resetb = gnd 2.7 0.01 ? a i dd operating (static) v i = v ih(ac) or v il(ac) , resetb = v dd 2.7 25 ma dynamic operating (clock only) resetb = v dd , v i = v ih(ac) or v il(ac) , clk and clkb switching 50 % duty cycle 2.7 328 ? a/clock mhz i ddd dynamic operating (per each data input) resetb = v dd , v i = v ih( ac) or v il(ac) , clk and clkb = switching 50% duty cycle ; one data input switching at half clock frequency, 50% duty cycle i o = 0 2.7 15 ?? /clock mhz/data input r oh output high i oh = - 20 ma 2.5 v to 2.7 7 13.5 20 ? r ol output low i ol = 20 ma 2.5 v to 2.7 7 20 ? r o(d) |r oh - r ol | each separate bit i o = 20 ma, t a = 25 ? c 2.6 4 ? data inputs 2.6 2.5 3.5 pf clk & clkb v i = v ref 310 mv, v icr = 1.25 v, v i(pp) = 360 mv 2.6 2.5 3.5 pf c i resetb v i = v dd or gnd 2.6 2.5 3.5 pf
a ugust 200 4 asm4sstvf16857 r ev 2.0 ddr 14 - bit registered buffer 8 of 16 timing requiremen ts (over recommended operating free - air temperature range, unless otherwise noted). guaranteed by design. not 100% production tested. * this parameter is not necessarily production tested. v ddq = 2.5v0.2v v ddq = 2.6v0.1v unit symbol parameters min ma x min max f clock clock frequency 200 270 mhz t w pulse duration, ck, cklb high or low 2.5 2.5 ns t act * differential inputs active time 22 22 ns t inact * differential inputs inactive time 22 22 ns setup time, fast slew rate 0.75 0.4 t s setup time, slow slew rate data before clk ? , clkb ? 0.9 0.6 ns ns hold time, fast slew rate 0.75 0.4 t h hold time, slow slew rate data after clk ? , clkb ? 0.9 0.6 ns ns t sl output slew rate, measurement point at 20% and 80% 1 4 1 4 v/ns note: 1. data inputs must be low for a minimum time of t act max, after which resetb is taken high. 2. data and clock inputs must be held at valid levels (not floating) for a minimum time of tinactmax after which resetb is taken low. 3. for data signal input slew ra te >=v/ns 4. for data signal input slew rate >=0.5 v/ns and < 1v/ns 5. clk,clkb signals input slew rates are >=1v/ns
a ugust 200 4 asm4sstvf16857 r ev 2.0 ddr 14 - bit registered buffer 9 of 16 switching characteristics - pc1600, pc2100, pc2700 (over recommended operating free - air temperature range unless otherwise noted.) vdd = 2.5 v 0.2 v symb ol from (input) to (output) min typ max units f max 200 C C pd clk, clkb q 1.1 2.8 ns t phl resetb q C C switching characteristics - pc3200 (over recommended operating free - air temperature range unless o therwise noted.) vdd = 2.6 v 0.1 v symbol from (input) to (output) min typ max units f max 280 mhz t pd clk, clkb q 1.1 2.2 ns t phl resetb q 5.0 ns
a ugust 200 4 asm4sstvf16857 r ev 2.0 ddr 14 - bit registered buffer 10 of 16 t w input v ih v il v ref v ref input v ih v il v ref v ref v icr timing input t s t h v i(pp) parameter measurement information (v dd = 2.5 v 0.2 v) v tt r l = 50 ? test point c l = 30 pf 1 load circuit from output under test 1 c l includes probe and jig capacitance. voltage and current waveforms in the following waveforms, note that all input pulses are supplied by generators having the following characteristics: prr ? 10 mhz, z o = 50 ? , input slew rate = 1 v/ns 20% (unless otherwise specified). the outputs are measured one at a time with one tr ansition per measurement. v tt = v ref = v ddq /2. v ih = v ref + 310 mv (ac voltage levels) for differential inputs. v ih = v dd for lvcmos input. v il = v ref - 310 mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos input. t plh and t phl are the same as t pd . input active and inactive times lvcmos resetb i dd 1 1 i dd tested with clock and data inputs held at v dd or gnd, and i o = 0 ma. v dd 0 v i ddh i ddl v dd /2 10% v dd /2 90% t inact t act input pulse duration setup and hold times propagation delay times
a ugust 200 4 asm4sstvf16857 r ev 2.0 ddr 14 - bit registered buffer 11 of 16 v icr v icr timing input output v tt v tt v oh v ol t plh t phl v i(pp) lvcmos resetb input output v ih v il v oh v ol t phl v dd /2 v tt
a ugust 200 4 asm4sstvf16857 r ev 2.0 ddr 14 - bit registered buffer 12 of 16 package dimensions (48 - pin tssop) 2 n index area e1 e e b a1 a d a2 c l aaa c 6.10 mm (240 mil) body, 0.50 mm (0.020 mil) pi tch tssop symbol millimeters inches min max min max a C C ? 8 ? 0 ? 8 ? aaa C C seating plane ? v ariations : n d (mm) d (inch) min max min max 48 12.40 12.60 0.488 0.496
a ugust 200 4 asm4sstvf16857 r ev 2.0 ddr 14 - bit registered buffer 13 of 16 package dimensions (alternate size) 2 n index area e1 e e b a1 a d a2 c l aaa c 4.40 mm (173 mil) body, 0.40 mm (16 mil) pitch tvsop symbol millimeters inches min max min max a C C ? 8 ? 0 ? 8 ? aaa C C variations : n d (mm) d (inch) min max min max 48 9.60 9.80 0.378 0.386 seating plane ?
a ugust 200 4 asm4sstvf16857 r ev 2.0 ddr 14 - bit registered buffer 14 of 16 or dering codes ordering number marking package type quantity per reel temperature asm4sstvf16857 - 48tt as4sstvf16857t 48 - pin tssop, tube 0 ? c to 70 ? c asm4sstvf16857 - 48tr as4sstvf16857t 48 - pin tssop, tape and reel 2500 0 ? c to 70 ? c asm4sstvf16857 - 48vt as4sst vf16857v 48 - pin tvsop, tube 0 ? c to 70 ? c asm4sstvf16857 - 48vr as4sstvf16857v 48 - pin tvsop, tape and reel 2500 0 ? c to 70 ? c
a ugust 200 4 asm4sstvf16857 r ev 2.0 ddr 14 - bit registered buffer 15 of 16 ? copyright 200 4 alliance semiconductor corporation. all rights res erved. our three - point logo, our name and intelliwatt are trademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document a nd its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive inf ormation for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product des cribed herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusively according to alliance's terms and condi tions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its prod ucts for use as critical components in life - supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life - supporting systems implies that the ma nufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. alliance semiconductor corporation 2595, augustine drive, santa clara, ca 95054 tel# 408 - 855 - 4900 fax: 408 - 855 - 4999 www.alsc.com copyright ? alliance semiconductor all rights reserved advance information part number: asm4sstvf16857 document version: v 2 .0
a ugust 200 4 asm4sstvf16857 r ev 2.0 ddr 14 - bit registered buffer 16 of 16

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